Integrated circuits (ICs) such as programmable ICs have become a popular platform for developing and prototyping IC designs. Programmable ICs refer to a type of IC that can be programmed to perform specified logic functions. One type of programmable IC, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of programmable IC is the complex programmable logic device or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable ICs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other programmable ICs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These programmable ICs are known as mask programmable devices. Programmable ICs can also be implemented in other ways, e.g., using fuse or antifuse technology. The phrase “programmable IC” can include, but is not limited to, these devices, and further may encompass devices that are only partially programmable. For example, one type of programmable IC includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Many programmable ICs include a variety of different types of circuit blocks. A “circuit block” can refer to a collection of components typically referred to, or thought of, as a single larger component by an end user of the programmable IC. For example, a BRAM, a DSP, and a CLB each is an example of a circuit block. These circuit blocks typically are highly configurable and include one or more components that can be bypassed depending upon the particular configuration of the circuit block that is selected by the end user of the programmable IC. With bypassable components, the number of timing paths through the circuit block and the delay of such timing paths can vary according to the configuration of the circuit block as determined by the data bits loaded into the programmable IC.
In order to provide the software development tools needed to implement circuit designs within programmable ICs, IC designers must document the timing paths within each circuit block within the programmable IC. Each timing path can be documented and added to a database that may be accessed by electronic design automation (EDA) tools, whether such tools are from the manufacturer of the programmable IC or other third party developers. End users of the EDA tools may then utilize the database of timing paths to analyze the timing of user specified designs that incorporate the circuit blocks.
Conventional analysis tools are unable to identify the various timing paths that may exist within a circuit block. This is particularly true of attribute sensitive timing paths, e.g., timing paths that conditionally exist according to whether components within the circuit block are bypassed given a user specified configuration of that circuit block. For example, commercially available static timing analysis tools are often unable to identify attribute dependent paths. In general, the static timing analysis tool must be run for each possible configuration of the circuit block. The number of combinations of attributes that specify the configuration of the circuit block can be significant and prohibitive in terms of manually trying to determine all possible configurations so as to identify all possible timing paths.
Thus, regardless of whether static timing analysis tools are used, IC designers are left with the daunting task of manually identifying timing paths of the circuit block based upon all possible configurations of the circuit block. Performing this analysis can be time consuming and tedious. Timing paths can be easily overlooked, particularly considering the complexity of modern circuit blocks and programmable ICs.